1. Field of the Invention
This invention relates to a logic gate circuit, particularly to a TTL (transistor-transistor logic).
2. Description of the Prior Art
In digital logic circuits, logic gates constructed as illustrated in FIGS. 1a and 1b are frequently used. These logic gates possess two input terminals and one output terminal. They fulfill a NAND function by a "not" signal of a first input and a second input signal or an OR function by a first input signal and a "not" signal of a second input. Let A stand for the logic at a first input terminal 1, B for the logic at a second input terminal 2, and Y for the logic at an output terminal 3, for example, and Y=A.multidot.B will be satisfied in the case of the logic gate of FIG. 1a and Y=A+B in the case of the logic gate of FIG. 1b. The four possible logic states for various combination of two inputs to these logic gates are shown in a truth table of Table 1.
TABLE 1 ______________________________________ Input 1 Input 2 Output 3 ______________________________________ H L H L L H H H H L H L ______________________________________
In the past, a TTL circuit of the type which fulfills the aforementioned functions, possesses a threshold circuit voltage equal to a voltage for two PN-junction stages (about 1.4 V), and uses a PNP transistor in the input stage in order to suppress the current possibly flowing to the input terminal when the input is of a low-level (hereinafter simply referred to as low-level input current). The circuit as shown in FIG. 2 is well known. In FIG. 2, reference numeral 1 denotes a first input terminal, 2 a second input terminal, 3 an output terminal, 4 an output part of an inverter circuit 10 which has the input terminal 1 as its input, 5 a power supply terminal, 6 a ground terminal, and 20 a NAND circuit having the input terminal 2 and the output 4 of the aforementioned inverter circuit 10 as its input. The transistors Q1, Q2, and Q3 are an input-stage transistor, an intermediate-stage transistor, and an output-stage transistor, respectively, of the inverter circuit 10, and the transistors Q4, Q5, Q6, Q7, Q8 and Q9 are an input-stage transistor, a phase split stage transistor, an off-buffer preceding stage transistor, an off-buffer succeeding stage transistor, an output-stage transistor, and a pulldown transistor, respectively, of the NAND circuit 20. In this circuit, for the purpose of suppressing the low-level input current, the transistors Q1 and Q4 are PNP transistors as described above. For all the transistors with the exception of the transistors Q1, Q4 and Q7, transistors are used whose base-collectors are clamped with Schottky barrier diodes (SBD) to prevent saturation. The diodes D1, D2, and D3 are a level shift diode, a speed-up SBD, and an output-level shift diode, respectively, of the inverter circuit 10, and the diodes D4, D5, and D6 are a level shift diode, a speed-up SBD, and an input gate SBD, respectively, of the NAND circuit 20. The resistors R1 to R9 typically have values of resistance as shown in Table 2.
TABLE 2 ______________________________________ Value of Resistance in Conventional Circuit Designation of resistor Value of resistance (k.OMEGA.) ______________________________________ R1 6 R2 6 R3 4 R4 6 R5 4 R6 0.05 R7 5 R8 1.5 R9 3 ______________________________________
In the circuit under discussion, as well known in the art, when the input at the input terminal 2 is in the low-level state (hereinafter simply referred to as "L"), the input-stage PNP transistor Q4 and the SBD D5 are rendered conductive and hence the base drive current for the phase split stage transistor Q5 disappears, so that the transistor Q5 and the output-stage transistor Q8 are turned off whereas the off-buffer transistors Q6 and Q7 are turned on, thereby producing a high level state (hereinafter simply referred to as "H") at the output terminal 3. When the input terminal 2 is in the "H" state, the transistor Q4 and the SBD D5 are turned off and, consequently, the operation of the phase split stage transistor Q5 is determined by the state of the input terminal 1, namely, by the state of the output 4 of the inverter circuit 10. More specifically, when the input terminal 1 is in the "H" state, the input-stage PNP transistor Q1 and the SBD D2 are turned off and the level shift diode D1, the intermediate-stage transistor Q2, and the output-stage transistor Q3 are turned on. Consequently, the electric current in the resistor R4 flows through the collector of the transistor Q3 through the diode D4 and the SBD D6. Similarly, when the input terminal 2 is in the state "L", therefore, the phase split stage transistor Q5 and the output-stage transistor Q8 of the NAND circuit 20 are turned off and the output terminal 3 assumes the "H" state. Conversely, when the input terminal 1 is in the state "L" state, the PNP transistor Q1 and the SBD D2 are turned on and the intermediate-stage transistor Q2 and the output-stage transistor Q3 are turned off, with the result that the electric current in the resistor R4 of the NAND circuit 20 flows through the diode D4 and serves as the base drive current for the phase split stage transistor Q5. As a result, the transistor Q5 and the output-stage transistor Q8 are turned on and the output terminal 3 assumes the state "L".
However, with the conventional TTL circuit shown in FIG. 2, in order to change the base level of the phase split stage transistor Q5 in the NAND circuit 20 in concert with the change in the level of the input terminal 1 when the input terminal 2 is in the state "H", it is necessary to send the signal at the input terminal 1 to the base of the phase split stage transistor Q5 via a number of elements including the PNP transistor Q1, the diode D1, and the transistors Q2 and Q3 of the inverter circuit 10 as well as the input gate SBD D6 of the NAND circuit 20. As a result, the delay time for signal transmission from the input terminal 1 to the base of the transistor Q5, namely, to the output terminal 3 (hereinafter simply referred to as "tpd") will be increased. In the case of the conventional circuit of FIG. 2 which has the values of resistance as shown in Table 2, for example, the turn-on time (hereinafter simply referred to as "tpHL") and the turn-off time (hereinafter simply referred to as "tpLH") which are required between the input terminal 2 and the output terminal 3 have relatively small values of 7 ns and 8 ns, respectively. The tpHL and the tpLH required between the input terminal 1 and the output terminal 3 have rather large values of 11 ns and 14 ns, respectively. The conventional circuit, therefore, has proved to be unsuitable for circuit switching.
Further, in the conventional circuit of FIG. 2, the "tpd" between the input terminal 1 and the base of the phase split stage transistor Q5 in the NAND circuit 20 is large as compared with the "tpd" between the input terminal 2 and the base of the transistor Q5 as described previously. Therefore, when both the input terminals 1 and 2 change from "L" to "H", the base of the phase split stage transistor Q5 assumes the state "H" until the output 4 of the inverter circuit 10 changes from "H" to "L" in response to the change of the input terminal 1 from "L" to "H", thereby turning on the transistor Q5 and consequently the output-stage transistor Q8. Thus, the output terminal 3 which should assume "H" is rendered "L" during the period of the above operation.
The conventional TTL circuit also requires, for transmission of the inverted signal at the input terminal to the base of the phase split stage transistor Q5 in the NAND circuit 20, ten circuit elements, i.e. three resistors, four diodes, and three transistors. The multiplicity of the circuit elements raises another problem of large power consumption in the circuit.
As described above, the conventional TTL circuit as shown in FIG. 2, which fulfills the functions of the logic gates of FIGS. 1a and 1b, possesses a threshold circuit voltage equal to a voltage for two PN-junction stage. In this arrangement, and uses a PNP transistor in the input stage, difficulties are encountered which involve the tendency to erroneous operation due to the large "tpd" in the longest path and the consequent difference between the values of "tpd" regarding the two inputs, the increase in the number of circuit elements, and the large power consumption.